EP2S90F1020C5N Altera Stratix II High-Performance FPGA for Telecom and Computing

EP2S90F1020C5N is a high-end FPGA from the Stratix II series by Altera  (now Intel). Manufactured on advanced 90nm SRAM technology, it features 90,960 Logic Elements (LEs) and 4,548 Adaptive Logic Modules (LABs). With up to 4,520 Kbits of embedded RAM and 12 PLLs, it supports complex logic, DSP processing, and high-bandwidth I/O. It offers 758 user I/O pins and operates at up to 609.76MHz. This commercial-grade device (0°C to 85°C) requires a 1.2V core supply. Although technically Obsolete, it remains widely used in legacy communications infrastructure and high-end industrial systems where long-term stability is required.

EP2S90F1020C5N Core Features

Logic Architecture： 90,960 Logic Elements (LEs) and 4,548 Adaptive Logic Modules (LABs) for high density digital logic design

Embedded Memory： 4,520,488 total RAM bits consisting of M4K and M-RAM blocks ideal for packet buffering and image processing

DSP Processing： 192 embedded 18x18 multipliers supporting high precision signal processing algorithms

High Speed I/O： Up to 758 user I O pins supporting multiple single ended and differential I O standards for large scale parallel interfaces

Clock Management： 12 built in phase locked loops for flexible clock synthesis and phase alignment

Maximum Frequency： Core logic operating frequency up to 609.76 MHz meeting high performance timing requirements

Process Technology： 90nm CMOS process with 1.5V to 3.3V multi voltage I O support

Package Type： 1020 pin FC-FBGA package 33 by 33 millimeters with 1 millimeter ball pitch

Temperature Rating： 0℃ to 85℃ commercial grade

Supply Voltage： Core voltage 1.15V to 1.25V (1.2V typical)

EP2S90F1020C5N Applications

Telecom and Network Infrastructure： Ideal for base stations and core routers handling complex protocol conversion and packet processing supporting high speed memory interfaces including DDR DDR2 SDRAM and QDRII+ SRAM

High Performance Computing and Prototyping： Leveraging high logic density of 90nm process for ASIC prototyping and running complex embedded systems including PowerPC SH 1960 system controller functions

Advanced Video and Image Processing： 90K logic elements combined with dedicated DSP resources for multi channel HD video codec scaling and recognition algorithms

Military and Aerospace： Commercial temperature range but with proven reliability for demanding ground radar signal processing and electronic warfare systems

Medical Imaging Systems： Ample RAM blocks and DSP resources for ultrasound beamforming and CT image reconstruction high throughput signal chains

EP2S90F1020C5N Key Advantages

Massive Logic Density： Core advantage of Stratix II series providing highest logic density of its time with 90K LE capacity for extremely complex digital logic reducing need for multiple small FPGAs

High Bandwidth I O and Memory Interfaces： Supports high speed external memories including DDR SDRAM DDR2 SDRAM RLDRAM II and QDRII+ SRAM for low latency data access

Mature High Speed Interface Capabilities： Supports LVPECL and LVDS differential I O standards for backplane communication and high speed ADC DAC data acquisition

Rich IP Ecosystem： Altera provides mature IP cores including RapidIO bridge controller Viterbi decoder and 32 64 bit PCI X interface significantly reducing development cycles

Stable Supply Chain Recognition： Although in obsolete lifecycle abundant global inventory supports equipment maintenance and long life project procurement requirements

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FAQ:

1. What is the EP2S90F1020C5N and its key specifications?
   This is an Altera Stratix II high‑performance FPGA built on a 90 nm process. It provides approximately 90,960 equivalent logic elements (LEs), 4.5 Mbits of embedded RAM (M4K and M‑RAM blocks), 192 dedicated 18×18 multipliers (equivalent to 384 9×9 multipliers), and 6 advanced PLLs. The device comes in a 1020‑pin FineLine BGA (FBGA1020) package, offering up to 742 user I/O pins. It operates from a 1.2 V core voltage, with the “‑5” speed grade indicating a standard speed bin, and “C” denoting a commercial temperature range (0 °C to +85 °C). The “N” suffix designates a lead‑free package. This FPGA is optimized for high‑performance telecom, computing, and data‑path applications where logic density and signal integrity are paramount.

2. How does the EP2S90F1020C5N differ from the faster EP2S90F1020I4N?
   The core logic, memory, and I/O resources are identical. The difference lies in speed grade and temperature range. The C5N variant has a ‑5 speed grade (standard performance) and operates over commercial temperature (0 °C to +85 °C). The I4N is a faster ‑4 speed grade and supports an industrial temperature range (‑40 °C to +100 °C). For telecom and computing environments that are temperature‑controlled and do not require the highest clock rates, the C5N provides a cost‑effective, reliable solution. If your design demands extra timing margin or must operate in harsh environments, the I4N is the preferred choice.

3. How many logic elements and DSP blocks does the EP2S90 offer, and why is that important for telecom and computing?
   With 90,960 logic elements and 192 18×18 multipliers, the EP2S90 can implement complex digital signal processing pipelines, high‑speed packet processing, and encryption engines commonly found in telecom infrastructure and computing accelerators. The DSP blocks can run up to 350 MHz, enabling real‑time FIR filters, FFTs, and channelization for baseband processing. The logic density is sufficient to host multiple soft‑core processors alongside custom hardware accelerators, making it a versatile platform for network line cards and compute blades.

4. What memory resources are available on the EP2S90F1020C5N?
   The FPGA contains 4.5 Mbits of embedded RAM, organized as M4K blocks (4 Kbits each, true dual‑port) and larger M‑RAM blocks (512 Kbits each). This memory architecture provides high‑bandwidth buffering for packet queues, look‑up tables, and instruction caches. The true dual‑port nature of the M4K blocks allows simultaneous read and write operations, which is critical for high‑throughput data‑path designs in routers, switches, and signal processing equipment.

5. How many I/O pins does the FBGA1020 package provide, and what standards are supported?
   The FBGA1020 package delivers up to 742 user I/O pins, supporting a wide range of single‑ended and differential standards: LVTTL, LVCMOS (1.2 V–3.3 V), SSTL, HSTL, LVDS, LVPECL, and others. Each I/O features programmable drive strength, slew rate, and on‑chip termination (OCT). This flexibility and high pin count make the device ideal for interfacing with multiple DDR/DDR2/QDR SRAM memories, SPI‑4.2, Utopia, and other parallel telecom buses without external termination resistors.

6. What is the maximum system clock speed achievable with the ‑5 speed grade?
   The ‑5 speed grade is a standard performance bin. In well‑optimized designs, system clock speeds of 150 MHz to 200 MHz are achievable for typical logic paths, while DSP blocks and memory can operate at higher internal frequencies. For telecom applications that often require 155.52 MHz (OC‑48) or 311.04 MHz (OC‑192) timing, the EP2S90‑5 comfortably meets these targets. If you need additional margin for more complex designs, the faster ‑4 or ‑3 grades are available.

7. How do I configure and program the EP2S90F1020C5N? What development tools are required?
   Configuration is stored in an external non‑volatile memory — typically an Altera EPC configuration device (EPC16/EPC8) or a MAX II CPLD. The FPGA loads its bitstream via Fast Passive Parallel (FPP), Active Serial (AS), or JTAG interfaces. Design entry, synthesis, and place‑and‑route are performed with Intel Quartus Prime Standard Edition (or the older Quartus II, which fully supports Stratix II). A USB‑Blaster download cable is used for programming. The built‑in SignalTap II logic analyzer allows real‑time debugging of internal signals.

8. What is the typical power consumption and what supply voltages are needed?
   The core voltage is 1.2 V, while I/O banks can be independently powered at 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V. Static power is under 1 W, and dynamic power depends on design complexity and clock frequency. A typical medium‑sized design may consume between 2 W and 6 W. The 90 nm low‑power process and programmable power options help keep thermal dissipation within manageable limits, even for high‑density telecom line cards.

9. How does the Stratix II compare to newer FPGA families like Stratix III or Cyclone IV?
   The Stratix II is a proven, mature 90 nm family that offers a strong balance of logic density, high‑speed I/O, and memory bandwidth. Stratix III (65 nm) provides higher density and lower power with advanced features like Programmable Power Technology. Cyclone IV E is a lower‑cost, lower‑density family without the high‑end DSP and memory resources of Stratix II. For legacy telecom and computing systems that require long‑term support, stability, and excellent signal integrity, the Stratix II remains a reliable and widely available choice.

10. What are the most typical telecom and computing applications for the EP2S90F1020C5N?
    This FPGA is ideally suited for telecom line cards (OC‑48/OC‑192 framers, packet processing), wireless baseband processing (channelization, digital up/down conversion), network switches and routers (queue management, traffic shaping), high‑performance computing accelerators, military communications, and test & measurement platforms. Its large logic capacity, abundant I/O, and DSP resources make it a versatile workhorse for any data‑intensive, high‑reliability computing environment.